ASIC/SoC Design Engineer

Responsibility

  • RTL design and define micro-architecture according to system requirements including performance, power, area, testability and reliability
  • Provide technical documents for all aspects of design with intended readers as architects, design engineers, design verification engineers, system validation engineers, and firmware engineers
  • Support DV engineers at block level and top level to ensure design quality
  • Support design integration activities including Lint, CDC, synthesis and ECO
  • Failure analysis in post-silicon validation
  • Evaluate design performance by architectural analysis and/or simulation

Qualifications

  • Deep knowledge of Digital Electronics
  • Real experience in the development of digital systems (FPGA-based design, ASIC/SoC design)
  • Strong logic design skill in RTL Verilog/SystemVerilog and experience from concept to tape-out is required
  • Knowledge of at least one of the industry standard simulators (Synopsys VCS, Siemens Modelsim/Questasim, Cadence Incisive/Xcellium)
  • Expertise in SoC interconnection interfaces (AMBA, Network Interconnect) is very desirable
  • Expertise in popular interfaces (UART, SPI, I2C) will be a plus
  • Expertise in NVMe, PCIe, NAND I/F, write/read datapath, ECC, data reliability algorithm, CPU
  • Experience of UVM verification methodology, regression system, and FPGA/Emulator validation methodology is desired
  • Understanding of SoC design flow – synthesis, ECO, DFT, floor planning, timing analysis, power analysis, and lower power design is desired
  • Proficiency in scripting language Python/Perl/Tcl/shell is desired
  • Expertise in system architecture for performance evaluation and optimization is desired for senior roles
  • Fluent communication skill for global operation, team player, believer of “Correct by Design” philosophy, ability to work creatively and analytically in a problem solving environment
  • Sufficient Linux skills
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